The present invention relates to a write operation of a semiconductor memory device, and more particularly, to a circuit and method for controlling loading of data to be written.
In general, a semiconductor memory device such as a Dynamic Random Access Memory (DRAM) is divided into a core region for processing data and a data input/output region for transceiving data with other semiconductor devices. A data block is provided in the data input/output region to buffer external data and transmit the buffered data to the core region.
FIG. 1 is a block diagram illustrating a conventional circuit for a write operation including a data block for transmitting external data to a core region. The circuit illustrates an example applied to a Dual Data Rate 3 (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) according to Joint Electron Device Engineering Council (JEDEC) specifications.
As shown, a data write operation is performed in such a manner that write drivers 32 and 34 of a memory bank 30 select data on a global bus 20 when a data block 10 receives data for writing and loads the data for writing on the global bus 20.
However, the data write operation increases power consumption by unnecessarily charging and discharging a Global Input/Output (GIO) bus which is the longest metal line in a semiconductor chip. The data write operation also causes coupling to a signal line adjacent to the GIO bus since the data block 10 writes data in the same way as a burst length is 8 even when a burst length of the data for writing is 4 and so unnecessarily occupies the GIO bus corresponding to the burst length 4. For example, according to the JEDEC specifications, in case of a burst length 4 (BL4) mode or a burst chop 4 (BC4) mode, the data block 10 loads four data on two GIO buses GIO_O<0:3> and GIO_O<4:7>, each of which can receive the four data by two using Input Output Sense Amplifiers (IOSA) 14 and 18 of a global input/output transmitting unit, and the write drivers 32 and 34 in an octet of the memory bank 30 select the data on the corresponding GIO buses and drive the data for writing.
Therefore, a new data write method is required to reduce power consumption due to unnecessary charging and discharging of the GIO bus in the semiconductor memory device and remove coupling caused in the signal line adjacent to the GIO bus.